1. Field of the Invention The present invention generally relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device that has bit lines formed in a semiconductor substrate and a method of manufacturing the semiconductor device.
2. Description of the Related Art
In recent years, non-volatile memories that are data-rewritable semiconductor devices are often used. In a flash memory, which is a typical non-volatile memory, each transistor forming a memory cell has a floating gate or an insulating film called a charge accumulating layer. As charges are accumulated in the charge accumulating layer, data is stored. An example of a flash memory having an insulating film as a charge accumulating layer is a SONOS (Silicon Oxide Nitride Oxide Silicon) flash memory that accumulates charges in the trapping layer in an ONO (Oxide/Nitride/Oxide) film. As a SONOS flash memory, U.S. Pat. No. 6,011,725 discloses a flash memory having virtual ground memory cells. Each of the virtual ground memory cells replaces the source and the drain with each other, and operates them in a symmetrical fashion.
FIG. 1 is a plan view of a memory cell of a conventional flash memory. It should be noted that an ONO film is not shown in FIG. 1. Bit lines 12 are formed with diffusion layers buried in a semiconductor substrate 10 extend in the vertical direction of FIG. 1, and word lines 23 extend in the width direction of the bit lines 12. Contact portions 42 are provided for each of the bit lines 12 at intervals of every several word lines 23 (every eight or sixteen word lines 23, for example). The contact portions 42 connect to wiring layers that are formed on the bit lines 12 and extend in the same direction as the bit lines 12.
Since the bit lines 12 are formed with diffusion layers, the resistivity of the bit lines 12 is high. If the bit lines 12 have high resistance, the write and erase characteristics of the charges (or data) accumulated in the trapping layer in the ONO film deteriorate. Therefore, the bit lines 12 are connected to the wiring layers formed with metal layers via the contact portions 42. In this manner, the resistance of the bit lines 12 can be made lower, and deterioration of the write and erase characteristics can be restrained.
As described above, a large number of contact portions 42 connecting to the bit lines 12 are provided, so as to obtain more uniform write and erase characteristics. However, the contact portions 42 add to the area. Therefore, the upper face of each of the bit lines 12 is silicided, so as to form a silicide layer 22a, as shown in FIG. 2A. Referring to FIG. 2A, an ONO film 20 formed with a tunnel oxide film 14, a trapping layer 16, and a top oxide film 18 is formed on the semiconductor substrate 10. Openings for forming the bit lines 12 are formed in the ONO film 20. With the openings serving as masks, the bit lines 12 and the silicide layers 22a are formed. In this manner, the resistance of the bit lines 12 can be made lower, and uniform write and erase characteristics can be obtained without a large number of contact portions 42. It should be understood here that, in this specification, “the resistance of the bit lines” is the resistance of the bit lines 12 and the silicide layers 22.
However, in a case where the silicide layers 22a are in contact with any portion of the semiconductor substrate 10 other than the bit lines 12, as shown in FIG. 2A, a current flows between the p-type semiconductor substrate 10 and the n-type bit lines 12 via the silicide layers 22a. Japanese Patent Application Publication No. 2005-57187 discloses a technique by which silicide layers 22b in the bit lines 12 are not in contact with the semiconductor substrate 10, as shown in FIG. 2B. By the technique disclosed in Japanese Patent Application Publication No. 2005-57187, the leakage current between the semiconductor substrate 10 and the bit lines 12 can be restrained, and accordingly, the resistance of the bit lines can be made lower.
Japanese Patent Application No. 10-284627 discloses a technique by which silicon oxide films including phosphorus (P) are formed on both sides of a gate insulating film.
However, in the flash memory disclosed in Japanese Patent Application Publication No. 2005-57187, the trapping layer 16 in the ONO film 20 is contaminated by the slurry that is used for polishing the interlayer insulating film and the metal material of the contact portions 42. When the trapping layer 16 is contaminated by organic matters such as Na and K included in the slurry, the charges accumulated in the trapping layer 16 are lost (the charge loss).